The present invention relates to a memory circuit incorporating a pair of bipolar transistors of emitter junction type and, more particularly, to a memory cell circuit using memory cells having non-linear collector loads.
Such a bipolar memory cell circuit of emitter coupled type has been known as having a pair of multi-emitter transistors having collector resistances connected to each collector of the multi-emitter transistors, and a clamp diode connected in parallel to each collector resistance. This type of circuit is shown, for example, in the specification of U.S. Pat. No. 3,537,078.
In the memory circuit having emitter coupled type memory cells, it is required to reduce as much as possible the stationary current non-selectively imparted to the memory cells, in order to reduce the power consumption of the memory circuit as a whole. On the other hand, the collector load resistance imparted to the memory cells is required to be diminished as much as possible, in order to increase the switching speed of the memory cells.
To meet these requirements, in the conventional memory cell circuit, it has been attempted to maintain the difference of output level between a pair of transistors which is imparted by a stationary current in the off-selection period at such a low level as 0.3 volt. The present inventors, however, have found out that this conventional memory circuit poses the following problems.
Referring to FIG. 4, the word line selection signal applied to the memory circuit and the writing pulse are represented by Ai and WE, respectively. Then, the delay time of the writing pulse WE is represented as set-up time T.sub.WSA, whereas the pulse width of the writing pulse WE is represented as writing time t.sub.W. The present inventors have found out that there is a relationship as shown in FIG. 3 between the writing time t.sub.W and set-up time t.sub.WSA.
More specifically, in FIG. 3, the curve A shows the characteristic of the writing time t.sub.W which permits a writing in any one of the memory cells arranged in a matrix-like form, while the curve B shows the characteristic of the writing time t.sub.W which makes it impossible to write in any one of the memory cells. The area S.sub.B defined by the curve B represents the region in which the writing is impossible. The writing time t.sub.W of the writing pulse determined by the characteristic curve B is the Not Write Pulse Width. The area Sc defined by the curves A and B represents the region in which a part of the memory cells is operative for the writing.
In order to write informations in any selected memory circuit, the writing time t.sub.W of writing pulse WE is determined to be longer than the time determined by the characteristic curve A.
In the known memory circuit, however, there is a problem that the Not Write Pulse width is about 0 ns in the set-up time t.sub.WSA around the rise of the word line signal Ai, as will be understood from the characteristic curve B of FIG. 3. The fact that the Not Write pulse width is 0 ns means that an erroneous writing is made in the memory circuit by a high-frequency noise N in the writing pulse having a peak value reaching the logic threshold voltage.